Blog Review: August 3

Laminated PCB; automotive grade; CMP; 3D NAND word line resistance; drop the phones.

Siemens Patrick Hope explains the growing importance of choosing the right laminate for PCB designs and how to read a material datasheet to compare important electrical, thermal and mechanical properties.

Synopsis’ Yankin Tanourhan argues that as the number of sensors integrated into automotive systems increases to enable new ADAS and autonomy capabilities, the integration of safety and quality into all stages of the design lifecycle becomes integral .

Cadences Paul McLellan explains chemical mechanical planarization (CMP), the wafer flattening process, and some of the issues that can arise during the process, such as dishing, pooling, and oxide loss.

Coventor’s Brett Lowe investigates the impact of void formation on wordline resistance in 3D NAND, which must be highly controlled to maintain the desired memory switching speed.

Ansys’ Alexander Pett explains Explicit Dynamic Analysis, a method of time integration used to perform dynamic simulations when speed matters, such as estimating damage incurred when a phone is dropped.

In a podcast, Arm’s Geof Charron chats with Arm’s Pablo Fraile, Unity’s Ralph Hauwert, and Sony’s Tetsuya Kimura about opportunities in the growing TV ecosystem, including what’s needed for future solutions, games and other interactive experiences, and c This is where future television is heading.

A Brewing Science The author explores how hybrid bonding can enable higher bandwidth and increased signal power and integrity and the key differences between SiOx/metal hybrid bonding and polymer/metal hybrid bonding.

A Rambus provides ways to implement Reliability, Availability, and Servicing (RAS) mechanisms that go beyond those included in the base PCI Express specification, including fault tolerance and layer-based monitoring .

Western Digital Ronni Shendard explores how scientists are able to image black holes using observations from a large number of networked telescopes and the massive amounts of data needed to produce images previously unimaginable.

And be sure to check out the blogs featured in the latest Systems & Design newsletter:

Editor Ed Sperling examines the CHIPS Act, concluding that while it addresses supply chain risk, it also raises important unanswered questions.

Technology Editor Brian Bailey observes that metrics for determining completeness are both incomplete and biased in both ML and UVM.

Synopsys’ Ian Land and Ricardo Borges examine how to ensure the survival of semiconductor components in orbit around our planet or while traveling in deep space.

Marta Martínez Vázquez of Renesas presents advances in radar technology that enable more sophisticated analysis, detection and tracking.

Cadence’s Frank Schirrmeister summarizes the rapid changes taking place in the aerospace/defense ecosystem.

Siemens EDA’s Dina Medhat uses a systematic methodology to verify latch-up prevention and ESD protection of 2.5D and 3D ICs.

Aakash Jani of Movellus warns that the clock distribution network consumes a significant portion of the physical design and verification budget.

Codasip’s Brett Cline finds enthusiastic support for the RISC-V ISA as architectural innovation takes over from traditional scaling.

Synopsys’ Ricardo Borges and Anand Thiruvengadam explain why memory optimization on advanced nodes requires it to be designed in the context of another technology.

Keysight’s Don Dingee offers techniques for smoothing out friction in a connected RF workflow.

WeiLii Tan and Jeff Dyck of Siemens EDA consider using ML to produce consistent, verifiable, and correct answers for SPICE-level IC verification.

Jesse Allen

Jesse Allen

(All posts)

Jesse Allen is a Knowledge Center Administrator and Editor at Semiconductor Engineering.

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