Blog review: October 20



Debug with real number models; early security; floating point; secondary channel attacks.

Siemens EDA Sumit vishwakarma promotes the elimination of preliminary bugs by using a real number model to describe an analog block as a discrete floating point model and allow it to simulate in a digital solver at near digital simulation speeds.

Synopsis’ Taylor armerding explains how including security in the software development process from the early planning stages will help IoT and other connected devices be more resilient to cyber attacks.

cadence Paul McLellan considers floating-point numbers, why they’re used, and some of the unexpected behaviors they exhibit.

A Rambus The author explains how secondary channel attacks work and details some of the more common attack methodologies, with particular emphasis on differential power analysis attacks and available countermeasures.

Ansys’ Jamie gooch emphasizes the importance of optics and simulation of the behavior of light at the nanophoton level and its manipulation with instruments and objectives for the design of cameras for consumer and ADAS applications.

Arms Reinhard Keil Advocates for the adoption of hybrid and cloud-based integrated development tools that provide continuous integration flows, model optimization for machine learning, and device provisioning for deployment.

EDD Alliance Bob smith talks with Nikos Zervas from CAST about the early days of the silicon IP market, when it started to take off and what has changed in the market since then.

Western Digital Ronni shendar examines the boom in small satellites, small satellites under 1,000 pounds that can be built much more easily than their larger counterparts, and how they use off-the-shelf components with software mechanisms to provide resilience instead of traditional hardened silicon by radiation.

In addition, do not miss the blogs featured in the latest Low Power-High Performance newsletter:

Moninder Singh of Synopsys explains why the complexity of the interface IP makes it difficult to maintain transistor netlist views that are logically equivalent to Verilog benchmarks.

Arm’s Remy Pottier argues that creating an ecosystem for ubiquitous computer systems will take a lot of trial and error.

Roland Jancke of Fraunhofer cautions that special attention should be paid to the non-functional properties of RF components.

Ansys’s Tyler Ferris identifies three places where electronics typically go wrong on a PCB.

Olaf Bendix of Infineon describes the steps to identify an appropriate gate driver IC based on the peak current and power dissipation requirements of an application.

Paul Karazuba of Rambus demonstrates how to minimize performance overhead while protecting high-value data transmitted through interconnects.

Cadence’s Shyam Sharma focuses on the requirements to watch out for when combining multiple individual DRAMs to create higher density memories.

Joe Davis of Siemens highlights the power analysis issues for large analog designs.

Anika Malhotra of Synopsys plans to use the IP-XACT integration standard to speed time to market and reduce costs.

Jesse Allen

Jesse Allen

(All posts)

Jesse Allen is the Administrator of the Knowledge Center and a Senior Editor at Semiconductor Engineering.


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